Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof.
Description of Related Art
A semiconductor device configured to have a chip stacked body mounted on a wiring substrate is conventionally proposed. The chip stacked body has a plurality of semiconductor chips stacked to one another, each of the semiconductor chips having through silicon vias or penetration electrodes penetrating therethrough. The semiconductor chips with through silicon vias have a small thickness of about 50 to 100 μm in view of a manufacturing process of the through silicon vias and are likely to have warpage.
When semiconductor chips with warpage are stacked to one another, a disconnection may occur between through silicon vias provided in one semiconductor chip and through silicon vias provided in another semiconductor chip. Such a disconnection tends to occur when the thickness of the semiconductor chips is small, 50 μm or less, for example.
Japanese Patent Application Laid-open No. 2008-294367 discloses a semiconductor device having a plurality of semiconductor chips stacked on a substrate, in which a reinforcing chip is provided to prevent the occurrence of warpage over an entire module due to stress generated by a difference in thermal contraction amounts between the substrate and the semiconductor chips during cooling, resulting from a difference in heating temperatures between the substrate and the semiconductor chips in a stacking process.
FIG. 9 is a cross-sectional view showing an example of a semiconductor chip having a through silicon via, which is applied to a conventional semiconductor device.
With reference to FIG. 9, a semiconductor chip 300 includes a semiconductor substrate 301, a circuit element layer 302 provided on a front surface 301a of the semiconductor substrate 301, a through silicon via 304 including a penetration via 303 that penetrates the semiconductor substrate 301, a front electrode 305 provided on one end of the through silicon via 304, a back electrode 306 provided on the other end of the through silicon via 304, a front resin layer 308 provided on a front surface 302a of the circuit element layer 302, and a back insulating layer 309 provided on a back surface 301b of the semiconductor substrate 301.
As described above, while the semiconductor chip 300 has the front resin layer 308 (polyimide resin, for example) on the front surface 302a of the circuit element layer 302 to protect the circuit element layer 302, only the back insulating layer 309 (a silicon nitride film, for example) is formed on the side of the back surface 301b of the semiconductor substrate 301.
When the semiconductor chips 300 with the configuration mentioned above are stacked and mounted by thermocompression bonding, the semiconductor chips 300 may warp because a difference in thermal expansion coefficients between the front resin layer 308 and the back insulating layer 309 is large.
While warpage occurring during cooling after heating at the time of mounting can be suppressed by the method disclosed in Japanese Patent Application Laid-open No. 2008-294367, suppression of warpage in semiconductor chips due to heating (heating for thermocompression bonding) in a stacking process is difficult.
When warpage occurs in the semiconductor chips 300 during heating and cooling in a stacking process, loose electrical connection between the semiconductor chips 300 may be increased, resulting in a lower yield of a semiconductor device.